# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s

--- |

  define i8 @zext_i1_to_i8(i1 %val) {
    %res = zext i1 %val to i8
    ret i8 %res
  }

  define i16 @zext_i1_to_i16(i1 %val) {
    %res = zext i1 %val to i16
    ret i16 %res
  }

  define i32 @zext_i1_to_i32(i1 %val) {
    %res = zext i1 %val to i32
    ret i32 %res
  }

  define i64 @zext_i1_to_i64(i1 %val) {
    %res = zext i1 %val to i64
    ret i64 %res
  }

  define i16 @zext_i8_to_i16(i8 %val) {
    %res = zext i8 %val to i16
    ret i16 %res
  }

  define i32 @zext_i8_to_i32(i8 %val) {
    %res = zext i8 %val to i32
    ret i32 %res
  }

  define i64 @zext_i8_to_i64(i8 %val) {
    %res = zext i8 %val to i64
    ret i64 %res
  }

  define i32 @zext_i16_to_i32(i16 %val) {
    %res = zext i16 %val to i32
    ret i32 %res
  }

  define i64 @zext_i16_to_i64(i16 %val) {
    %res = zext i16 %val to i64
    ret i64 %res
  }

  define i64 @zext_i32_to_i64(i32 %val) {
    %res = zext i32 %val to i64
    ret i64 %res
  }

...
---
name:            zext_i1_to_i8
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i1_to_i8
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
    ; CHECK: $al = COPY [[AND]](s8)
    ; CHECK: RET 0, implicit $al
    %1:_(s32) = COPY $edi
    %0:_(s1) = G_TRUNC %1(s32)
    %2:_(s8) = G_ZEXT %0(s1)
    $al = COPY %2(s8)
    RET 0, implicit $al

...
---
name:            zext_i1_to_i16
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i1_to_i16
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
    ; CHECK: $ax = COPY [[AND]](s16)
    ; CHECK: RET 0, implicit $ax
    %1:_(s32) = COPY $edi
    %0:_(s1) = G_TRUNC %1(s32)
    %2:_(s16) = G_ZEXT %0(s1)
    $ax = COPY %2(s16)
    RET 0, implicit $ax

...
---
name:            zext_i1_to_i32
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i1_to_i32
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK: $eax = COPY [[AND]](s32)
    ; CHECK: RET 0, implicit $eax
    %1:_(s32) = COPY $edi
    %0:_(s1) = G_TRUNC %1(s32)
    %2:_(s32) = G_ZEXT %0(s1)
    $eax = COPY %2(s32)
    RET 0, implicit $eax

...
---
name:            zext_i1_to_i64
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i1_to_i64
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
    ; CHECK: $rax = COPY [[AND]](s64)
    ; CHECK: RET 0, implicit $rax
    %1:_(s32) = COPY $edi
    %0:_(s1) = G_TRUNC %1(s32)
    %2:_(s64) = G_ZEXT %0(s1)
    $rax = COPY %2(s64)
    RET 0, implicit $rax

...
---
name:            zext_i8_to_i16
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i8_to_i16
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
    ; CHECK: $ax = COPY [[AND]](s16)
    ; CHECK: RET 0, implicit $ax
    %1:_(s32) = COPY $edi
    %0:_(s8) = G_TRUNC %1(s32)
    %2:_(s16) = G_ZEXT %0(s8)
    $ax = COPY %2(s16)
    RET 0, implicit $ax

...
---
name:            zext_i8_to_i32
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i8_to_i32
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK: $eax = COPY [[AND]](s32)
    ; CHECK: RET 0, implicit $eax
    %1:_(s32) = COPY $edi
    %0:_(s8) = G_TRUNC %1(s32)
    %2:_(s32) = G_ZEXT %0(s8)
    $eax = COPY %2(s32)
    RET 0, implicit $eax

...
---
name:            zext_i8_to_i64
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i8_to_i64
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
    ; CHECK: $rax = COPY [[AND]](s64)
    ; CHECK: RET 0, implicit $rax
    %1:_(s32) = COPY $edi
    %0:_(s8) = G_TRUNC %1(s32)
    %2:_(s64) = G_ZEXT %0(s8)
    $rax = COPY %2(s64)
    RET 0, implicit $rax

...
---
name:            zext_i16_to_i32
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i16_to_i32
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK: $eax = COPY [[AND]](s32)
    ; CHECK: RET 0, implicit $eax
    %1:_(s32) = COPY $edi
    %0:_(s16) = G_TRUNC %1(s32)
    %2:_(s32) = G_ZEXT %0(s16)
    $eax = COPY %2(s32)
    RET 0, implicit $eax

...
---
name:            zext_i16_to_i64
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i16_to_i64
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
    ; CHECK: $rax = COPY [[AND]](s64)
    ; CHECK: RET 0, implicit $rax
    %1:_(s32) = COPY $edi
    %0:_(s16) = G_TRUNC %1(s32)
    %2:_(s64) = G_ZEXT %0(s16)
    $rax = COPY %2(s64)
    RET 0, implicit $rax

...
---
name:            zext_i32_to_i64
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i32_to_i64
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
    ; CHECK: $rax = COPY [[ZEXT]](s64)
    ; CHECK: RET 0, implicit $rax
    %0:_(s32) = COPY $edi
    %1:_(s64) = G_ZEXT %0(s32)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
